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| Semiconductor MSM5267B-15 Semiconductor MSM5267B-15 33-BIT VFD SEGMENT DRIVER GENERAL DESCRIPTION The MSM5267B-15 is a CMOS multi-digit display driver and consisting of a 34-bit shift register, a 33-bit latch, and a 33-bit VF tube driver. FEATURES * * * * * * * * * Complete static operation to ensure stability against noise. 3 or 4-signal line connection with microcomputers. Direct driver of VF tubes (8 outputs of high-current drive, 25 outputs of low-current drive) Capability of self-load mode. Low power consumption. Signal power supply and operating voltage range of 8V to 18V. 40-pin Plastic DIP (DIP40-P-600) 44-pin "V" Plastic QFP (QFP44-P-910-VK) 44-pin Plastic QFJ (PLCC) (QFJ44-P-S650) 1/9 Semiconductor BLOCK DIAGRAM DATA CLOCK D R 33 Q D R 32 Q D R 31 Q D R 1 Q D R 0 MSM5267B-15 Q DATA OUT LOAD ENABLE L I L O I L O I L O I O OUTPUT1 OUTPUT2 VDD OUTPUT3 OUTPUT32 VDD VSS Q D DQ L R R O L L L NMOS I L O VDD PMOS OUTPUT33 BLANK 2/9 MSM5267B-15 PIN CONFIGURATION Semiconductor 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 MSM 5267B-15 LOAD ENABLE 33 32 31 30 29 28 27 26 25 24 23 OUTPUT 3 OUTPUT 4 OUTPUT 5 OUTPUT 6 OUTPUT 7 * OUTPUT 8 OUTPUT 9 OUTPUT10 OUTPUT11 OUTPUT12 OUTPUT 33 DATA OUT OUTPUT 2 OUTPUT 1 CLOCK (NC) BLANK DATA GND VDD 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 OUTPUT 32 OUTPUT 31 OUTPUT 30 OUTPUT 29 OUTPUT 28 * OUTPUT 27 OUTPUT 26 OUTPUT 25 OUTPUT 24 OUTPUT 23 1 2 3 4 5 6 7 8 9 10 11 OUTPUT 13 OUTPUT 14 OUTPUT 15 OUTPUT 16 OUTPUT 17 OUTPUT 18 OUTPUT 19 OUTPUT 20 OUTPUT 21 Note) Pin 17 and Pin 39 are internally connected to VDD. Therefore, those pins can not be connected to any other pin than VDD. 3/9 OUTPUT 22 (NC) Semiconductor PIN DISCRIPTION PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name VDD Data Clock Output 1 Output 2 Output 3 Output 4 Otuput 5 Otuput 6 Otuput 7 Output 8 Output 9 Output 10 Output 11 Output 12 Output 13 Output 14 Output 15 Otuput 16 Otuput 17 Otuput 18 Output 19 Output 20 Output 21 Output 22 Output 23 Output 24 Output 25 Output 26 Otuput 27 Otuput 28 Otuput 29 Output 30 Output 31 Output 32 Output 33 Data Out Load Enable Vss Blank Input Data Acquisition Terminal Input Clock Terminal Output Shift Register 32 Output Shift Register 21 Output Shift Register 22 Output Shift Register 23 Output Shift Register 30 Output Shift Register 13 Output Shift Register 14 Output Shift Register 15 Output Shift Register 1 Output Shift Register 33 Output Shift Register 5 Output Shift Register 6 Output Shift Register 7 Output Shift Register 28 Output Shift Register 27 Output Shift Register 31 Output Shift Register 18 Output Shift Register 2 Output Shift Register 10 Output Shift Register 26 Output Shift Register 29 Output Shift Register 3 Output Shift Register 8 Output Shift Register 9 Output Shift Register 4 Output Shift Register 11 Output Shift Register 16 Output Shift Register 17 Output Shift Register 12 Output Shift Register 19 Output Shift Register 24 Output Shift Register 25 Output Shift Register 20 Output Data Shift Register Comments Input Positive Supply Voltage Terminal MSM5267B-15 Input for Loading Word into Data Latch from Data Shift Register Ground Potential Terminal Input for Turning Output Drivers off 4/9 MSM5267B-15 ELECTRICAL CHARACTERISTICS * Absolute Maximum Ratings Semiconductor Ta=25C, Unless otherwise specified Parameter Supply voltage Input voltage Operating Temperature Storage Temperature Symbol VDD VI Ta Tst Condition - - - - Min -0.3 -0.3 -40 -65 Max 20 VDD + 0.3 85 150 Unit V V C C AC CHARACTERISTICS Ta=-40C to +85C, VDD=8V to 18V Unless otherwise specified Condition MIN MAX Units - Either positive or negative CL=100pF, t=20% to 80% or 80% to 20% tR tS tH tODB tODL PRSR PWL CL=100pF VDD=8V CL=100pF VDD=8V - - of VDD VDD=8V or VDD=18V - - 1 200 - - 0.001 1.6 - - 7 8 10 - S nS S S V/S S - 5 S - 2.5 160 - kHz S Characteristics Clock Frequency Clock Pulse Width Slew Rate Outputs; (1-33) Data Setup Time Data Hold Time Output Delay from Blank Output Delay from Load Power on Reset Slew Rate Load Pulse Width Symbol FC PWC 5/9 Semiconductor * Timing Chart MSM5267B-15 fC CLOCK 3.5V - 0.8V - DATA IN 3.5V - 0.8V - LOAD ENABLE 3.5V - 0.8V - BLANK 3.5V - OUTPUT 3.5V - 0.8V - tODL tODL tODB ts pwC pwC th ts th pwL 6/9 MSM5267B-15 DC CHARACTERISTICS Semiconductor Ta= -40 to 85C Unless otherwise specified Characterristic High Level input Voltage Low Level Input Voltage High Input Current (PIN 2,3,38) Low Input Current (PIN 2,3,38) High Input Current (PIN 40) Low Input Current (PIN 40) IIL2 VDD=8 to 18V, VI=VSS VDD=8 to 16V, All Outputs open Supply Current IDD Ta= -40C, 25C VDD=8 to 16V, All Outputs open Ta=85C Low Current Output Drivers (ON) (PIN4-16, 25-36) High Current Output Drivers (ON)(PIN 17-24) Output Drivers (OFF) (PIN 4-36) High Voltage Data out (PIN 37) Low Voltage Dataout (PIN 37) VOLD VOHD VOL VDD=9.5V, IOL=1A/500A VOH2 VDD=9.5V, IOH= -30mA VDD=9.5V, IOH= -6mA VOH1 VDD=9.5V, IOH= -1.5mA Ta= 25C -40C Ta= 85C Ta= 25C -40C Ta= 85C Ta= 25C -40C Ta= 85C -5 - - VDD-0.3 -125 10 7 - V IIH2 IIL1 VDD=8 to 18V, VI=VSS VDD=8 to 18V, VI=3.5V - -5 -1 -125 IIH1 VIL VIH Symbpl VDD=8 to 18V VDD=8 to 18V VDD=8 to 18V, VI=VDD Conditions MIN 3.5 -0.3 MAX VDD+0.3 0.8 Unit V V A A A A mA mA - 1 VDD-0.5 VDD-0.3 VDD-0.5 VDD-2.0 VDD-2.5 - - - - - - Vss + 0.2 / Vss + 5 - Vss + 0.4 VOH2 V V V VDD9.5V, IOHD= -500A IOLD=1A VDD-5 - V V 7/9 Semiconductor FUNCTIONAL DESCRIPTION MSM5267B-15 * Data Input The data pattern (33 bits) supplied to the device through this input control the output driver state (On or Off). 1. A high level turns the output driver on. 2. A low level turns the output driver off. * Clock Input A Positive transition of the clock loads and shifts the data. This input also has a Schmitt trigger which provides 0.3 volts of hysteresis. * Blanking Input A low-level voltage at this pin turns the output drivers off; an internal pull up is provided on this pin. * Load Enable A high-level at this input transfers the data from the shift register to the data latch, and sets the shift register to zero. First data bit read-in stored in a shift register #1, the last data bit read-in is stored in a shift register #33. When the shift registers are full, a high voltage level applied to the load enable input will transfer the data from the shift register to the data latch, and then to the output. The device has 34 shift registers and 33 data latches as shown in the functional block diagram. There are two modes of operation: VDD FROM MICROPROCESSOR 1 2 3 40 38 DATA OUT 37 39 33 OUTPUTS DATA CLOCK BLANK LOAD ENABLE * Self-Load Mode In this mode Data Out (pin37) is connected to Load Enable (pin38), and the data word is constructed with 33 bits (including the one self-load bit set to logic 1). At the 34th clock pulse, the data is transferred from the shift register to the data latch and the output drivers. Before the next clock pulse, the registers are zeroed. * Non-Self-Load Mode In this mode, the Data Out and the Load Enable pins are not connected, and the Load Enable input is controlled by an external source. (There are two types of operation in this mode.) 1. The data word consists of 34 bits (including one self-load bit). To transfer data from the shift registers to the data latch, a high-level voltage is applied to the Load Enable pin before the rise of the clock pulse following the 34th clock pulse. 2. The data word consists of 33 bits without the self-load bit. To transfer the data, a high voltage level is applied to the Load Enable pin before the rise of the 34th clock pulse. 8/9 MSM5267B-15 Semiconductor VDD FROM MICROPROCESSOR 1 2 3 40 38 DATA OUT 33 OUTPUTS DATA CLOCK BLANK LOAD ENABLE 39 37 When the display driver is used in a cascade configuration, a filler bit must be inserted between each group of 33 data bits. The filler bit must be logic 1 when used with the self-loading mode and a logic 0 when used in the non-self-loading mode. VDD DATA CLOCK BLANK LOAD ENABLE 39 2 3 40 38 1 37 DATA OUT VDD DATA 2 CLOCK 3 BLANK 40 LOAD ENABLE 38 39 1 37 DATA OUT When the cascaded devices are used in self-load mode. The Data Out pin of the last device must be connected to the Load Enable pin of all devices as shown in the above figure. When two display drivers are cascaded, sufficient on-chip time delays allow the system to operate within the specification of the device and work in a system. Up to 10 driver inputs may be connected to the Data Out pin (pin37) of the last device. Information furnished by OKI is believed to be accurate and reliable. However, no responsibility is assumed by OKI for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of OKI. 9/9 |
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